80C196EA Datasheet, PDF (15/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
Name
CS2:0#
EA#
EPA16:0
EPORT.7:0
EXTINT
Type
O
I
I/O
I/O
I
Table 4. Signal Descriptions (Sheet 3 of 8)
Description
Chip-select Lines 0–2
The active-low output CSx# is asserted during an external memory cycle when
the address to be accessed is in the range programmed for chip select x. If the
external memory address is outside the range assigned to the three chip
selects, no chip-select output is asserted and the bus configuration defaults to
the CS2# values.
Immediately following reset, CS0# is automatically assigned to the range
FF2000 FF20FFH (1F2000 1F20FFH if external).
CS2:0# share package pins with EPORT.7:5.
External Access
This input determines whether memory accesses to special-purpose and pro-
gram memory partitions (FF2000 FF3FFFH) are directed to internal or external
memory. These accesses are directed to internal memory if EA# is held high
and to external memory if EA# is held low. For an access to any other memory
location, the value of EA# is irrelevant.
EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect.
On devices with no internal nonvolatile memory, always connect EA# to V_SS.
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
EPA16:0 share package pins with the following signals: EPA0/P7.0/T1CLK,
EPA1/P7.1/T1RST, EPA2/P7.2/T2CLK, EPA3/P7.3/T2RST,
EPA4/P7.4/T3CLK, EPA5/P7.5/T3RST, EPA6/P7.6/T4CLK,
EPA7/P7.7/T4RST, EPA8/P8.0, EPA9/P8.1, EPA10/P8.2, EPA11/P8.3,
EPA12/P8.4, EPA13/P8.5, EPA14/P8.6, EPA15/P8.7, and EPA16/P10.4.
Extended Addressing Port
This is a standard 8-bit, bidirectional port.
EPORT.4:0 share package pins with A20:16. EPORT7:5 share package pins
with CS2:0#.
External Interrupt
In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt
pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum
high time is one state time.
In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the
device to resume normal operation. The interrupt need not be enabled, but the
pin must be configured as a special-function input. If the EXTINT interrupt is
enabled, the CPU executes the interrupt service routine. Otherwise, the CPU
executes the instruction that immediately follows the command that invoked the
power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to resume nor-
mal operation.
EXTINT shares a package pin with P2.2.
ADVANCE INFORMATION
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