80C196EA Datasheet, PDF (26/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
T_RLAZ
T_LLWL
T_QVWH
T_CHWH
T_WLWH
T_WHQX
T_WHLH
T_WHBX
T_WHAX
T_RHBX
T_RHAX
T_WHSH
T_RHSH
T_AVYV
T_CLYX
RD# Low to Address Float
ALE Low to WR# Low
Data Stable to WR# Rising Edge
CLKOUT High to WR# Rising Edge
WR# Low to WR# High
Data Hold after WR# High
WR# High to ALE High
BHE#, INST Hold after WR# High
AD15:8, CSx# Hold after WR# High
BHE#, INST Hold after RD# High
AD15:8, CSx# Hold after RD# High
A20:0, CSx# Hold after WR# High
A20:0, CSx# Hold after RD# High
AD15:0 Valid to READY Setup
READY Hold after CLKOUT Low
t – 12
t – 14
– 10
t – 10
t – 20
t – 15
t–4
t–4
t–5
t–5
0
0
0
5
10
t + 10
2t – 40
2t – 40
ns
ns
ns (2)
ns (9)
ns (2)
ns
ns
ns
ns (6)
ns
ns (6)
ns
ns
ns (4)
ns
(5, 7, 9)
T_YLYH
Non-READY Time
No Upper Limit
ns
NOTES:
1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz
can be applied with an external clock source.
2. If wait states are used, add 2t × n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
4. When forcing wait states using the BUSCON register, add 2t × n.
5. Exceeding the maximum specification causes additional wait states.
6. 8-bit bus only.
7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
wait state is required.
8. Device is static by design but has been tested only down to 20 MHz.
9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Table 8. AC Timing Symbol Definitions
A^† Address
Signals
L ALE
W WR#, WRH#, WRL# H
B BHE#
Q Output Data
X XTAL1
L
C CLKOUT
R RD#
Y READY
V
D Input Data
S
CSx#
X
Z
† _{Address bus (demultiplexed mode) or address/data bus (multiplexed mode)}
Conditions
High
Low
Valid
No Longer Valid
Floating
20
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