XC2269I Datasheet, PDF (99/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Electrical Parameters
4.6.2 Definition of Internal Timing
The internal operation of the XC2269I is controlled by the internal system clock f_SYS.
Because the system clock signal f_SYS can be generated from a number of internal and
external sources using different mechanisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate f_SYS. This must be considered when calculating the timing
for the XC2269I.
Phase Locked Loop Operation (1:N)
f_IN
f
SYS
Direct Clock Drive (1:1)
f_IN
TCS
f_SYS
Prescaler Operation (N:1)
f
IN
TCS
f_SYS
TCS
M C_XC2X_CLOCKGEN
Figure 16 Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 16 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Data Sheet
99
V1.3, 2014-07