XC2269I Datasheet, PDF (41/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Functional Description
3
Functional Description
The architecture of the XC2269I combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources. This bus structure enhances overall system performance by enabling the
concurrent operation of several subsystems of the XC2269I.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC2269I.
3.1
Memory Subsystem and Organization
The memory space of the XC2269I is configured in the von Neumann architecture. In this
architecture all internal and external resources, including code memory, data memory,
registers and I/O ports, are organized in the same linear address space.
Table 8
XC2269I Memory Map ¹⁾
Address Area
Start Loc. End Loc.
IMB register space
Reserved
Reserved for EPSRAM
Emulated PSRAM
FF’FF00_H
F0’0000_H
E9’0000_H
E8’0000_H
FF’FFFF_H
FF’FEFF_H
EF’FFFF_H
E8’FFFF_H
Reserved for PSRAM
PSRAM
E1’0000_H E7’FFFF_H
E0’0000_H E0’FFFF_H
Reserved for Flash
Flash 4
Flash 3
Flash 2
Flash 1
Flash 0
External memory area
External IO area⁴⁾
D1’0000_H
D0’0000_H
CC’0000_H
C8’0000_H
C4’0000_H
C0’0000_H
40’0000_H
21’0000_H
DF’FFFF_H
D0’FFFF_H
CF’FFFF_H
CB’FFFF_H
C7’FFFF_H
C3’FFFF_H
BF’FFFF_H
3F’FFFF_H
Area Size²⁾
256 Bytes
< 1 Mbyte
448 Kbytes
up to
64 Kbytes
448 Kbytes
up to
64 Kbytes
448 Kbytes
64 Kbytes
256 Kbytes
256 Kbytes
256 Kbytes
256 Kbytes³⁾
8 Mbytes
1 984 Kbytes
Notes
Minus IMB registers
Mirrors EPSRAM
With Flash timing
Mirrors PSRAM
Program SRAM
Minus res. seg.
Data Sheet
41
V1.3, 2014-07