XC2269I Datasheet, PDF (111/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Electrical Parameters
Note: The term CLKOUT refers to the reference clock output signal which is generated
by selecting f_SYS as the source signal for the clock output signal EXTCLK on pin
P2.8 and by enabling the high-speed clock driver on this pin.
Variable Memory Cycles
External bus cycles of the XC2269I are executed in five consecutive cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module
using the READY handshake input.
This table provides a summary of the phases and the ranges for their length.
Table 34 Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter Valid Values Unit
Address setup phase, the standard duration of this tpAB
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
1 … 2 (5) TCS
Command delay phase
tpC
0…3
TCS
Write Data setup/MUX Tristate phase
tpD
0…1
TCS
Access phase
tpE
1 … 32
TCS
Address/Write Data hold phase
tpF
0…3
TCS
Note: The bandwidth of a parameter (from minimum to maximum value) covers the
whole operating range (temperature, voltage) as well as process variations. Within
a given device, however, this bandwidth is smaller than the specified range. This
is also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Note: Operating Conditions apply; C_L = 20 pF.
Data Sheet
111
V1.3, 2014-07