XC2269I Datasheet, PDF (113/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Electrical Parameters
Table 36 EBC External Bus Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Output valid delay for RD, t₁₀ CC −
WR(L/H)
11
20
ns
Output valid delay for
BHE, ALE
t₁₁ CC −
10
21
ns
Address output valid delay t₁₂ CC −
for A23 ... A0
11
22
ns
Address output valid delay t₁₃ CC −
for AD15 ... AD0 (MUX
mode)
10
22
ns
Output valid delay for CS t₁₄ CC −
Data output valid delay for t₁₅ CC −
AD15 ... AD0 (write data,
MUX mode)
10
13
ns
10
22
ns
Data output valid delay for t₁₆ CC −
D15 ... D0 (write data,
DEMUX mode)
10
22
ns
Output hold time for RD, t₂₀ CC -2
8
WR(L/H)
10
ns
Output hold time for BHE, t₂₁ CC -2
8
ALE
10
ns
Address output hold time t₂₃ CC -3
8
for AD15 ... AD0
10
ns
Output hold time for CS t₂₄ CC -3
8
Data output hold time for t₂₅ CC -3
8
D15 ... D0 and AD15 ...
AD0
11
ns
10
ns
Input setup time for
t₃₀ SR 29
17
−
ns
READY, D15 ... D0, AD15
... AD0
Input hold time READY, t₃₁ SR 0
-9
−
ns
D15 ... D0, AD15 ... AD0¹⁾
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Data Sheet
113
V1.3, 2014-07