English
Language : 

XC2269I Datasheet, PDF (89/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller
XC2269I
XC2000 Family Derivatives / Premium Line
Electrical Parameters
2) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 µs. Result below 10% (66H).
4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high
temperature. Result above 80% (332H).
5) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
Table 21 ADC Parameters for Upper Voltage Range
Parameter
Symbol
Values
Min. Typ. Max.
Input resistance of the
RAIN CC −
selected analog channel
0.9 1.5
Input resistance of the
reference input
RAREF
−
CC
0.5 1
Differential Non-Linearity |EADNL| −
Error 2)3)4)5)
CC
Gain Error 2)3)4)5)
|EAGAIN| −
CC
Integral Non-Linearity
2)3)4)5)
|EAINL| −
CC
Offset Error 2)3)4)5)
|EAOFF| −
CC
Total Unadjusted Error 3)4) |TUE| −
CC
Analog clock frequency fADCI SR 2
2
1.5 3.0
0.5 3.5
1.5 3.0
1.0 4.0
2.5 4
−
20
−
17.5
Wakeup time from analog tWAF CC −
−
7
powerdown, fast mode
Wakeup time from analog tWAS CC −
−
11.5
powerdown, slow mode
Unit Note /
Test Condition
kΩ not subject to
production test
1)
kΩ not subject to
production test
1)
LSB not subject to
production test
LSB not subject to
production test
LSB not subject to
production test
LSB not subject to
production test
LSB 6)
MHz
MHz
Std. reference
input (VAREF)
Alt. reference
input (CH0)
μs
μs
Data Sheet
89
V1.3, 2014-07