XC2269I Datasheet, PDF (125/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Electrical Parameters
Table 43 DAP Interface Timing for Lower Voltage Range
Parameter
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t₁₁ SR 25¹⁾
t₁₂ SR 8
t₁₃ SR 8
t₁₄ SR −
t₁₅ SR −
t₁₆ SR 6
Values
Typ. Max.
−
−
−
−
−
−
−
4
−
4
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns pad_type= stan
dard
DAP1 hold after DAP0 t₁₇ SR 6
−
−
ns pad_type= stan
rising edge
dard
DAP1 valid per DAP0
t₁₉ CC 12
17
−
clock period²⁾
ns pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t₁₁ ≥ t_SYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t₁₁
0.5 VDDP
t₁₅
t₁₂
t₁₃
Figure 25 Test Clock Timing (DAP0)
0.9 V_DDP
t₁₄
0.1 V_DDP
MC_DAP0
Data Sheet
125
V1.3, 2014-07