XC2269I Datasheet, PDF (97/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Electrical Parameters
Table 27 Flash Parameters (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Number of erase cycles N_ER SR −
−
15 000 cycle t_RET ≥ 5 years;
s Valid when
using Flash
module 4 for
data storage.
−
−
1 000 cycle t_RET ≥ 20 years
s
1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one
Flash module or from PSRAM. The Flash module that delivers code/data can, of course, not be
erased/programmed.
2) Flash module 4 can be erased/programmed while code is executed and/or data is read from any other Flash
module.
3) Value of IMB_IMBCTRL.WSFLASH.
4) Value of IMB_IMBCTRL.WSFLE.
Set bit STMEM0.SFAR = 1 before selecting a system frequency above 80 MHz to avoid an inadvertent
waitstate violation after an application reset (caused by the default setting).
5) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
Access to the XC2269I Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Flash access via the cacheable Flash address space requires one additional waitstate
in case of a cache miss, while the cache access (in case of a cache hit) requires no
waitstate at all.
Data Sheet
97
V1.3, 2014-07