XC2269I Datasheet, PDF (48/134 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2269I
XC2000 Family Derivatives / Premium Line
Functional Description
With this hardware most XC2269I instructions are executed in a single machine cycle of
ns @ -MHz CPU clock. For example, shift and rotate instructions are always processed
during one machine cycle, no matter how many bits are shifted. Also, multiplication and
most MAC instructions execute in one cycle. All multiple-cycle instructions have been
optimized so that they can be executed very fast; for example, a 32-/16-bit division is
started within 4 cycles while the remaining cycles are executed in the background.
Another pipeline optimization, the branch target prediction, eliminates the execution time
of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 word-
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided for storage of temporary data. The system
stack can be allocated to any location within the address space (preferably in the on-chip
RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during
each stack access to detect stack overflow or underflow.
The high performance of the CPU hardware implementation can be best utilized by the
programmer with the highly efficient XC2269I instruction set. This includes the following
instruction classes:
• Standard Arithmetic Instructions
• DSP-Oriented Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
48
V1.3, 2014-07