HYB25D128400AT Datasheet, PDF (9/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Pin Configuration
Table 3 Pin Definitions and Functions
Symbol
Type
Function
CK, CK
Clock: CK and CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative edge
of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing).
CKE
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power-Down and Self Refresh operation (all banks idle), or Active
Power-Down (row Active in any bank). CKE is synchronous for power down entry
and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE
must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers,
excluding CKE, are disabled during self refresh.
CS
Chip Select: All commands are masked when CS is registered HIGH. CS
provides for external bank selection on systems with multiple banks. CS is
considered part of the command code. The standard pinout includes one CS pin.
RAS, CAS, WE
Command Inputs: RAS, CAS and WE (along with CS) define the command
being entered.
DM
UDM, LDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading. For the ×16, LDM corresponds to the
data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write
or Precharge command is being applied. BA0 and BA1 also determines if the
mode register or extended mode register is to be accessed during a MRS or
EMRS cycle.
A0 - A11
Input
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA0, BA1. The address inputs also provide the op-code
during a Mode Register Set command.
DQ
Input
Data Input/Output: Data bus.
DQS
UDQS,LDQS
Input
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.For the ×16, LDQS
corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-
DQ15.
NC
Input
No Connect: No internal electrical connection is present.
V_DDQ
V_SSQ
Input
Input/Out-
put
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
V_DD
Input/Out- Power Supply: 2.5V ± 0.2V.
put
V_SS
V_DDQ V_REF
Supply
Ground
SSTL_2 reference voltage: (V_DDQ / 2)
Data Sheet
9
Rev. 1.06, 2004-01
09192003-LFQ1-R60G