HYB25D128400AT Datasheet, PDF (58/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 17 AC Operating Conditions¹⁾
Parameter
Symbol
Input High (Logic 1) Voltage, DQ, DQS and V_IH(AC)
DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and V_IL(AC)
DM Signals
Input Differential Voltage, CK and CK
Inputs
V_ID(AC)
Input Closing Point Voltage, CK and CK V_IX(AC)
Inputs
Values
min.
max.
V_REF + 0.31 –
–
V_REF - 0.31
0.7
V_DDQ + 0.6
0.5 × V_DDQ
- 0.2
0.5 × V_DDQ
+ 0.2
Unit
V
Note/
Test Condition
2)3)
V
2)3)
V
2)3)4)
V
2)3)5)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until V_REF stabilizes.
4) V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of V_IX is expected to equal 0.5 × V_DDQ of the transmitting device and must track variations in the DC level of the
same.
Table 18 AC Timing - Absolute Specifications –8/–7/-6
Parameter
Symbol
–8
–7
DDR200
DDR266A
Min. Max. Min. Max.
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
t_AC
t_DQSCK
t_CH
t_CL
t_HP
t_CK3
t_CK2.5
t_CK2
t_CK1.5
t_DH
t_DS
t_IPW
–0.8 +0.8 –0.75 +0.75
–0.8 +0.8 –0.75 +0.75
0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55
min. (t_CL, t_CH) min. (t_CL, t_CH)
8 12
7
12
8 12
7
12
10 12
7.5 12
10 12
——
0.6 —
0.5 —
0.6 —
0.5 —
2.5 —
2.2 —
DQ and DM input pulse width (each t_DIPW
input)
2.0 —
1.75 —
Data-out high-impedance time from t_HZ
CK/CK
–0.8 +0.8 –0.75 +0.75
Data-out low-impedance time from
CK/CK
Write command to 1^st DQS latching
transition
t_LZ
t_DQSS
–0.8 +0.8
0.75 1.25
–0.75 +0.75
0.75 1.25
–6
DDR333
Min. Max.
–0.7 +0.7
–0.6 +0.6
0.45 0.55
0.45 0.55
min. (t_CL, t_CH)
6
12
6
12
7.5 12
0.45 —
0.45 —
2.2 —
1.75 —
–0.7 +0.7
–0.7 +0.7
0.75 1.25
—
+0.40
Note/
Test Conditi
on ¹⁾
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 3.0 ^2)3)4)5)
CL = 2.5 ^2)3)4)5)
CL = 2.0 ^2)3)4)5)
CL = 1.5 ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
Data Sheet
58
Rev. 1.06, 2004-01
09192003-LFQ1-R60G