HYB25D128400AT Datasheet, PDF (65/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

5
Timing Diagrams
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Timing Diagrams
DQS
DQ
DM
t_DQSL
t_DQSH
t_DH
t_DS
DI n
t_DH
t_DS
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Figure 37 Data Input (Write), Timing Burst Length = 4
Don’t Care
DQS
DQ
t_{DQSQ max}
t_QH
t_QH (Data output hold time from DQS)
t_DQSQ and t_QH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.
t._DQSQ and t_QH both apply to each of the four relevant edges of DQS.
t_{DQSQ max.} is used to determine the worst case setup time for controller data capture.
t_QH is used to determine the worst case hold time for controller data capture.
Figure 38 Data Output (Read), Timing Burst Length = 4
Data Sheet
65
Rev. 1.06, 2004-01
09192003-LFQ1-R60G