HYB25D128400AT Datasheet, PDF (46/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Table 7 Truth Table 2: Clock Enable (CKE)
Current State CKE n-1 CKEn
Command n
Action n
Notes
Previous Current
Cycle
Cycle
Self Refresh L
L
X
Self Refresh L
H
Deselect or NOP
Maintain Self-Refresh
–
Exit Self-Refresh
1)
Power Down L
L
X
Maintain Power-Down
–
Power Down L
H
Deselect or NOP
Exit Power-Down
–
All Banks Idle H
L
Deselect or NOP
Precharge Power-Down Entry –
All Banks Idle H
L
AUTO REFRESH
Self Refresh Entry
–
Bank(s) Active H
L
Deselect or NOP
Active Power-Down Entry
–
H
H
See “Truth Table 3:
–
–
Current State Bank n -
Command to Bank n (same
bank)” on Page 47
1) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t_XSNR) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Note:
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved
Data Sheet
46
Rev. 1.06, 2004-01
09192003-LFQ1-R60G