HYB25D128400AT Datasheet, PDF (12/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
12
12
14
A0-A11,
BA0, BA1
14
2
2
9
Column-Address
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
4096
Bank0
Memory
Array
(4096 x 256x 32)
Sense Amplifiers
I/O Gating
DM Mask Logic
256
(x32)
Column
Decoder
8
COL0
1
32
32
32
Data
16
16
16
DQS
1
Generator
COL0 _Input
DQS
Register
Write ^{Mask 1}
FIFO
&
Drivers
1
2
32 ¹⁶
1
1
1
16
16
clk
out
clk
in
Data
16
16
CK,
COL0
CK
2
DQ0-DQ15,
DM
LDQS, UDQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the
operation of the device; it does not represent an actual circuit implementation.
Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to
match the load of the bidirectional DQ , UDQS and LDQS signals.
Figure 4 Block Diagram (8Mb × 16)
Data Sheet
12
Rev. 1.06, 2004-01
09192003-LFQ1-R60G