HYB25D128400AT Datasheet, PDF (61/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 19 AC Timing for DDR266(A) - Applicable Specs in Clock Cycles
Parameter
Symbol DDR266(A) @CL = 2 Units Notes ¹⁾
Mode register set command cycle time
Write preamble
Active to Precharge command
Active to Active/Auto-refresh command period
t_MRD
t_WPRE
t_RAS
t_RC
Auto-refresh to Active/Auto-refresh command period t_RFC
Active to Read or Write delay
t_RCD
Precharge command period
t_RP
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
Min.
2
0.25
6
9
8
10
3
2
3
2
2
2
5
1
17
200
Max.
—
—
16000
—
—
—
—
—
—
—
—
—
—
—
—
—
t_CK
2)3)4)5)6)
t_CK
2) to 6)
t_CK
2) to 6)
t_CK DDR266A ^{2) to 6)}
t_CK DDR266 ^{2) to 6)}
t_CK
2) to 6)
t_CK DDR266A ^{2) to 6)}
t_CK DDR266 ^{2) to 6)}
t_CK DDR266A ^{2) to 6)}
t_CK DDR266 ^{2) to 6)}
t_CK
2) to 6)
t_CK
2) to 6)
t_CK
2) to 6)
t_CK
2) to 6)
t_CK
2) to 6)
t_CK
2) to 6)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V
2) Input slew rate = 1 V/ns.
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT.
6) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
61
Rev. 1.06, 2004-01
09192003-LFQ1-R60G