HYB25D128400AT Datasheet, PDF (14/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
MR
Mode Register Definition
(BA[1:0] = 00_B)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A13
0
0
reg. addr
MODE
w
CL
BT
BL
w
w
w
Field Bits Type Description
BL [2:0] w
Burst Length
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.
Note: All other bit combinations are RESERVED.
BT 3
w
CL [6:4] w
000
001 2
010 4
011 8
100
101
110
111
Burst Type
See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2.
0 Sequential
1 Interleaved
CAS Latency
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note: All other bit combinations are RESERVED.
MODE [13:7] w
000
001
010 2
011 (3.0 Optional, not covered by this data sheet)
100
101
110 1.5 for DDR200 components only
101 2.5
Operating Mode
000 Valid Normal Operation without DLL Reset
010 Valid Normal Operation without DLL Reset
001 Test Mode
See Chapter 3.2.4.
Note: All other bit combinations are RESERVED.
3.2.1 Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Data Sheet
14
Rev. 1.06, 2004-01
09192003-LFQ1-R60G