HYB25D128400AT Datasheet, PDF (10/79 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
12
12
14
A0-A11,
BA0, BA1
14
2
2
11 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
4096
Bank0
Memory
Array
(4096 x 1024 x 8)
Sense Amplifiers
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
10
COL0
1
8
8
8
Data
4
4
4
DQS
Generator
COL0 _Input
Register
Write ^{Mask 1}
1
FIFO
&
1
2
1
Drivers _{8 4}
4
clk
out
clk
in
Data
4
4
1
DQS
1
4
CK,
COL0
CK
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the
operation of the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load
of the bidirectional DQ and DQS signals.
Figure 2 Block Diagram (32Mb × 4)
Data Sheet
10
Rev. 1.06, 2004-01
09192003-LFQ1-R60G