XC164CS-16F Datasheet, PDF (73/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Electrical Parameters
Table 22 External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
Min.
Max.
Output valid delay for:
RD, WR(L/H)
tc₁₀ CC 1
13
ns
Output valid delay for:
BHE, ALE
tc₁₁ CC -1
7
ns
Output valid delay for:
A23 … A16, A15 … A0 (on PORT1)
tc₁₂ CC 1
16
ns
Output valid delay for:
A15 … A0 (on PORT0)
tc₁₃ CC 3
16
ns
Output valid delay for:
CS
tc₁₄ CC 1
14
ns
Output valid delay for:
D15 … D0 (write data, MUX-mode)
tc₁₅ CC 3
17
ns
Output valid delay for:
tc₁₆ CC 3
D15 … D0 (write data, DEMUX-mode)
17
ns
Output hold time for:
RD, WR(L/H)
tc₂₀ CC -3
3
ns
Output hold time for:
BHE, ALE
tc₂₁ CC 0
8
ns
Output hold time for:
A23 … A16, A15 … A0 (on PORT0)
tc₂₃ CC 1
13
ns
Output hold time for:
CS
tc₂₄ CC -3
3
ns
Output hold time for:
D15 … D0 (write data)
tc₂₅ CC 1
13
ns
Input setup time for:
D15 … D0 (read data)
tc₃₀ SR 24
–
ns
Input hold time
D15 … D0 (read data)¹⁾
tc₃₁ SR -5
–
ns
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Note: The shaded parameters have been verified by characterization.
They are not subject to production test.
Data Sheet
71
V2.2, 2006-03