XC164CS-16F Datasheet, PDF (23/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
CPU
Prefetch
U n it
Branch
U n it
FIFO
ID X 0
ID X 1
QX0
QX1
+/-
M u ltip ly
U n it
+/-
MAH
MAC
PMU
CSP
IP
CPUCON1
CPUCON2
R e tu rn
Stack
IFU
VECSEG
TFR
Injection/
Exception
Handler
2-Stage
Prefetch
P ip e lin e
5-Stage
P ip e lin e
IP IP
QR0
QR1
+/-
MRW
MCW
MSW
MAL
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
ADU
Division Unit
M ultiply Unit
MDC
PSW
MDH
ZEROS
Bit-M ask-G en.
B a rre l-S h ifte r
+/-
MDL
ONES
ALU
CP
RR1 _{15 5}
RR1 _14R41 5
R14
GGPPRRs _s
GPRs
RR1 ₁
RR00R 1
R0
RF
B u ffe r
WB
DMU
PSRAM
F la s h /R O M
DPRAM
R15
R14
GPRs
R1
R0
DSRAM
EBC
P e rip h e ra ls
m ca04917_x.vsd
Figure 4 CPU Block Diagram
Based on these hardware provisions, most of the XC164’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
Data Sheet
21
V2.2, 2006-03