XC164CS-16F Datasheet, PDF (21/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Functional Description
bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7,
RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller.
Table 3
XC164 Memory Map¹⁾
Address Area
Flash register space
Reserved (Acc. trap)
Start Loc.
FF’F000_H
F8’0000_H
End Loc.
FF’FFFF_H
FF’EFFF_H
Area Size²⁾
4 Kbytes
Notes
Flash only³⁾
< 0.5 Mbytes Minus Flash register
space
Reserved for PSRAM
Program SRAM
Reserved for program
memory
E0’0800_H
E0’0000_H
C2’0000_H
F7’FFFF_H
E0’07FF_H
DF’FFFF_H
< 1.5 Mbytes Minus PSRAM
2 Kbytes
Maximum
< 2 Mbytes Minus Flash/ROM
Program Flash/ROM
Reserved
External memory area
C0’0000_H
BF’0000_H
40’0000_H
C1’FFFF_H
BF’FFFF_H
BE’FFFF_H
128 Kbytes
64 Kbytes
< 8 Mbytes
4)
–
Minus reserved
segment
External IO area⁵⁾
20’0800_H 3F’FFFF_H < 2 Mbytes Minus TwinCAN
TwinCAN registers
20’0000_H 20’07FF_H 2 Kbytes
–
External memory area 01’0000_H
Data RAMs and SFRs 00’8000_H
1F’FFFF_H < 2 Mbytes
00’FFFF_H 32 Kbytes
Minus segment 0
Partly used⁴⁾
External memory area 00’0000_H 00’7FFF_H 32 Kbytes –
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) Depends on the respective derivative. The derivatives are listed in Table 1.
5) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
19
V2.2, 2006-03