XC164CS-16F Datasheet, PDF (66/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Electrical Parameters
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal f_MC. Therefore,
the number of VCO cycles can be represented as K × N, where N is the number of
consecutive f_MC cycles (TCM).
For a period of N × TCM the accumulated PLL jitter is defined by the deviation D_N:
D_N [ns] = ±(1.5 + 6.32 × N / f_MC); f_MC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D₃ = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: D_Nmax [ns] = ±(1.5 + 600 / (K × f_MC)).
Acc. jitter D_N
ns
±8
K = 12 K = 8
K = 15 K = 10
K=6 K=5
±7
±6
±5 10 MHz
20 MHz
±4
±3
±2
40 MHz
±1
0
01
5
10
15
20
25 N
MCD05566
Figure 16 Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Data Sheet
64
V2.2, 2006-03