XC164CS-16F Datasheet, PDF (68/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Electrical Parameters
4.4.2 On-chip Flash Operation
The XC164’s Flash module delivers data within a fixed access time (see Table 17).
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time t_ACC of the Flash array. Therefore, the required Flash waitstates depend on the
available speed grade as well as on the actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
Table 17 Flash Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
Min. Typ. Max.
Flash module access time
t_ACC CC –
–
50 ns
Programming time per 128-byte block t_PR CC –
2¹⁾
5
ms
Erase time per sector
t_ER CC –
200¹⁾ 500 ms
1) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), devices can be
operated with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 18 indicates the interrelation of waitstates and system frequency.
Table 18 Flash Access Waitstates
Required Waitstates
0 WS (WSFLASH = 00_B)
1 WS (WSFLASH = 01_B)
Frequency Range
f_CPU ≤ 20 MHz
f_CPU ≤ 40 MHz
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-16F20F devices).
Data Sheet
66
V2.2, 2006-03