XC164CS-16F Datasheet, PDF (29/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Functional Description
The XC164 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector Trap Trap
Location¹⁾ Number Priority
Reset Functions:
–
• Hardware Reset
• Software Reset
• Watchdog Timer
Overflow
RESET
xx’0000_H 00_H
III
RESET
xx’0000_H 00_H
III
RESET
xx’0000_H 00_H
III
Class A Hardware Traps:
• Non-Maskable Interrupt NMI
NMITRAP xx’0008_H 02_H
II
• Stack Overflow
STKOF STOTRAP xx’0010_H 04_H
II
• Stack Underflow
STKUF STUTRAP xx’0018_H 06_H
II
• Software Break
SOFTBRK SBRKTRAP xx’0020_H 08_H
II
Class B Hardware Traps:
• Undefined Opcode
• PMI Access Error
• Protected Instruction
Fault
UNDOPC BTRAP
PACER BTRAP
PRTFLT BTRAP
xx’0028_H 0A_H
I
xx’0028_H 0A_H
I
xx’0028_H 0A_H
I
• Illegal Word Operand
Access
ILLOPA
BTRAP
xx’0028_H 0A_H
I
Reserved
–
–
[2C_H - 3C_H] [0B_H -
0F_H]
Software Traps
–
–
Any
Any
• TRAP Instruction
[xx’0000_H - [00_H -
xx’01FC_H] 7F_H]
in steps of
4_H
1) Register VECSEG defines the segment where the vector table is located to.
–
Current
CPU
Priority
Data Sheet
27
V2.2, 2006-03