XC164CS-16F Datasheet, PDF (65/78 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-16
Derivatives
Electrical Parameters
CPU and EBC are clocked with the CPU clock signal f_CPU. The CPU clock can have the
same frequency as the master clock (f_CPU = f_MC) or can be the master clock divided by
two: f_CPU = f_MC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal f_SYS which has the same
frequency as the CPU clock signal f_CPU.
Bypass Operation
When bypass operation is configured (PLLCTRL = 0x_B) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f_MC = f_OSC / ((PLLIDIV+1) × (PLLODIV+1)).
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of f_MC
directly follows the frequency of f_OSC so the high and low time of f_MC is defined by the duty
cycle of the input clock f_OSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f_MC = f_OSC / ((3 + 1) × (14 + 1)) = f_OSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11_B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (f_MC = f_OSC × F) which results from the input divider, the multiplication factor, and
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f_MC is constantly adjusted so it
is locked to f_OSC. The slight variation causes a jitter of f_MC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because f_CPU is derived from
f_MC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 16).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
Data Sheet
63
V2.2, 2006-03