TC1736 Datasheet, PDF (51/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1736
Introduction
• Input multiplexer width of 16 possible analog input channels (not all of them are
necessarily available on pins)
• V_AREF and 1 alternative reference input at channel 0
• Programmable sample time (in periods of f_ADCI)
• Wide range of accepted analog clock frequencies f_ADCI
• Multiplexer test mode (channel 7 input can be connected to ground via a resistor for
test purposes during run time by specific control bit)
• Power saving mechanisms
Features of the Digital Part of each ADC Kernel
• Independent result registers (16 independent registers)
• 5 conversion request sources (e.g. for external events, auto-scan, programmable
sequence, etc.)
• Synchronization of the ADC kernels for concurrent conversion starts
• Control an external analog multiplexer, respecting the additional set up time
• Programmable sampling times for different channels
• Possibility to cancel running conversions on demand with automatic restart
• Flexible interrupt generation (possibility of DMA support)
• Limit checking to reduce interrupt load
• Programmable data reduction filter by adding conversion results
• Support of conversion data FIFO
• Support of suspend and power down modes
• Individually programmable reference selection for each channel (with exception of
dedicated channels always referring to V_AREF
2.5.8 Fast Analog to Digital Converter (FADC)
General Features
• Extreme fast conversion, 21 cycles of f_FADC clock (262.5 ns @ f_FADC = 80 MHz)
• 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• Successive approximation conversion method
• Two differential input channels with impedance control overlaid with ADC1 inputs
• Each differential input channel can also be used as single-ended input
• Offset and gain calibration support for each channel
• Programmable gain of 1, 2, 4, or 8 for each channel
• Free-running (Channel Timers) or triggered conversion modes
• Trigger and gating control for external signals
• Built-in Channel Timers for internal triggering
• Channel timer request periods independently selectable for each channel
• Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
Data Sheet
47
V1.1, 2009-08