TC1736 Datasheet, PDF (23/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1736
Introduction
2.4.3 System Timer
The TC1736’s STM is designed for global system timing applications requiring both high
precision and long range.
Features
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Flexible interrupt generation based on compare match with partial STM content
• Driven by maximum 80 MHz (= f_SYS, default after reset = f_SYS/2)
• Counting starts automatically after a reset operation
• STM registers are reset by an application reset if bit ARSTDIS.STMDIS is cleared. If
bit ARSTDIS.STMDIS is set, the STM registers are not reset.¹⁾.
• STM can be halted in debug/suspend mode
Special STM register semantics provide synchronous views of the entire 56-bit counter,
or 32-bit subsets at different levels of resolution.
The maximum clock period is 2⁵⁶ × f_STM. At f_STM = 80 MHz, for example, the STM counts
28.56 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life time of a system without overflowing.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the TC1736
(initiated by writing an appropriate value to STM_CLC register), the STM clock is
stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading of
the STM content, a capture register (STM_CAP) is implemented. It latches the content
of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5
is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time
when the lower part is read. The second read operation would then read the content of
the STM_CAP to get the complete timer value.
The STM can also be read in sections from seven registers, STM_TIM0 through
STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can
be viewed as individual 32-bit timers, each with a different resolution and timing range.
The content of the 56-bit System Timer can be compared against the content of two
compare values stored in the STM_CMP0 and STM_CMP1 registers. Service requests
1) “STM registers” means all registers except STM_CLC, STM_SRC0, and STM_SRC1.
Data Sheet
19
V1.1, 2009-08