TC1736 Datasheet, PDF (31/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1736
Introduction
• Dynamic correction of single-bit errors during read access.
• Transfer rate in burst mode: One 64-bit double-word per clock cycle.
• Sector architecture:
– Eight 16 Kbyte, one 128 Kbyte and three 256 Kbyte sectors.
– Each sector separately erasable.
– Each sector lockable for protection against erase and program (write protection).
• One additional configuration sector (not accessible to the user).
• Optional read protection for whole Flash, with sophisticated read access supervision.
Combined with whole Flash write protection — thus supporting protection against
Trojan horse programs.
• Sector specific write protection with support of re-programmability or locked forever.
• Comfortable password checking for temporary disable of write or read protection.
• User controlled configuration blocks (UCB) in configuration sector for keywords and
for sector-specific lock bits (one block for every user; up to three users).
• Pad supply voltage (V_DDP) also used for program and erase (no VPP pin).
• Efficient 256 byte page program operation.
• All Flash operations controlled by CPU per command sequences (unlock sequences)
for protection against unintended operation.
• End-of-busy as well as error reporting with interrupt and bus error trap.
• Write state machine for automatic program and erase, including verification of
operation quality.
• Support of margin check.
• Delivery in erased state (read all zeros).
• Global and sector status information.
• Overlay support with SRAM for calibration applications.
• Configurable wait state selection for different CPU frequencies.
• Endurance = 1000; minimum 1000 program/erase cycles per physical sector;
reduced endurance of 100 per 16 KB sector.
• Operating lifetime (incl. Retention): 20 years with endurance=1000.
• For further operating conditions see data sheet section “Flash Memory Parameters”.
Data Flash Features and Functions
• 32 Kbyte on-chip Flash, configured in two independent Flash banks of equal size.
• 64 bit read interface.
• Erase/program one bank while data read access from the other bank.
• Programming one bank while erasing the other bank using an automatic
suspend/resume function.
• Dynamic correction of single-bit errors during read access.
• Sector architecture:
– Two sectors of equal size.
– Each sector separately erasable.
• 128 byte pages to be written in one step.
Data Sheet
27
V1.1, 2009-08