TC1736 Datasheet, PDF (25/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1736
Introduction
2.4.4 System Control Unit
The following SCU introduction gives an overview about the TC1736 System Control
Unit (SCU).
2.4.4.1 Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1736.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption.
2.4.4.2 Features of the Watchdog Timer
The main features of the WDT are summarized here.
• 16-bit Watchdog counter
• Selectable input frequency: f_FPI/256 or f_FPI/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated Password Access mechanism with fixed and user-definable password
fields
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled
• Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1736 is held in reset until a system / class 0 reset
occurs.
2.4.4.3 Reset Operation
The following reset request triggers are available:
• 1 External power-on hardware reset request trigger; PORST, (cold reset)
• 2 External System Request reset triggers; ESR0 and ESR1 (warm reset)
• Watchdog Timer (WDT) reset request trigger, (warm reset)
• Software reset (SW), (warm reset)
• Debug (OCDS) reset request trigger, (warm reset)
• JTAG reset (special reset)
Data Sheet
21
V1.1, 2009-08