TLE8110EE Datasheet, PDF (47/72 Pages) Infineon Technologies AG – Smart Multichannel Low Side Switch with Parallel Control and SPI Interface

FLEX
Smart Multi-Channel Switch
Control of the device
Field
PAR
ADDR
DATA
Bits
15
14:12
11:0
Description
PAR - Parity Bit
1: odd number of '1' in data and address field
0: even number of '1' in data and address field
Address
Address which has bin addressed
Data
Content of Address or feedback Data
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at
SPI signal SO will contain the requested information. A new command can be executed in the second frame.
12.2.3.2 2x8-bit protocol
Each Cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned
at the same time by the S_SO. The content of the S_SO frame is dependent of the previous command which has
been sent to S_SI and the content of the actual content of S_SI: The first Upper Byte send to S_SI controls the
content of the Lower Byte actual returned by S_SO. The Lower Byte send to S_SI controls the Lower Byte in S_SO
of the next frame. (see Figure 27 ).
Upper
Byte
Lower
Byte
Upper
TOR _Byte
DO
Figure 27 2x8-bit protocol
Upper
Byte
Lower
Byte
Upper
TOR _Byte
Lower
Byte
Upper
Byte
Lower
Byte
Upper
TOR _Byte
Lower
Byte
SPI_Protocol_2x8bit.vsd
Data Sheet
47
Rev. 1.0, 2009-06-15