TLE8110EE Datasheet, PDF (45/72 Pages) Infineon Technologies AG – Smart Multichannel Low Side Switch with Parallel Control and SPI Interface

FLEX
Smart Multi-Channel Switch
Control of the device
S_CLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (S_SI) transfers data is shifted into the register on
the falling edge of S_CLK while the serial output (S_SO) shifts the information out on the rising edge of the serial
clock. It is essential that the S_CLK pin is in low state whenever chip select CS makes any transition.
S_SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. The bit at the S_SI Pin is read on the
falling edge of S_CLK.
S_SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. S_SO is in high impedance state until the S_CS
pin goes to low state.The next bits will appear at the S_SO pin following the rising edge of S_CLK.
12.2.2 Daisy Chain Capability
The SPI-Interface of TLE8110EE provides daisy chain capability. In this configuration several devices are
activated by the same S_CS signal. The S_SI line of one device is connected with the S_SO line of another device
(see Figure 25), which builds a chain. The ends of the chain are connected with the output and input of the master
device, S_SO and S_SI respectively. The master device provides the master clock CLK, which is connected to the
S_CLK line of each device in the chain. By each clock edge on S_CLK, one bit is shifted into the S_SI. The bit
shifted out can be seen at SO. After 16 S_CLK cycles, the data transfer for one device has been finished. In single
chip configuration, the S_CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device 1 has been shifted in to device 2. Example: When using three devices
in daisy chain, three times 16 bits have to be shifted through the devices. After that, the S_CS line must go high
(see Figure 25).
SI
SO
CS
CLK
time
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
SPI_DasyChain2.emf
Figure 25 Principle example for Data Transfer in Daisy Chain Configuration
Note: Due to the integrated modulo 8 counter, 8 bit and 16 bit devices can be used in one daisy chain.
12.2.3 SPI Protocol
The device contains two protocol styles which are applied dependent of the used commands. There is the
standard 16-bit protocol and the 2x8-bit protocol. Both protocols can appear also be mixed.
12.2.3.1 16-bit protocol
Each Cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned
at the same time by the S_SO The content of the S_SO frame is dependent on the previous command which has
been sent to S_SI. Read Command (R/W = R) returns one cycle later the content of the addresses register. (see
Figure 26 ).
Data Sheet
45
Rev. 1.0, 2009-06-15