C165UTAH Datasheet, PDF (461/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
System Control Unit (CSCU)
Note: In parallel to the XPER control with XPERCON register, the visibility of XPER
address spaces also is controlled with the BUSACT bits in respective XBCON
registers (in the C166 core)
Note: The XPER configuration is additionally controlled by means of flexible peripheral
management control (see Peripheral Management Module below) for power
reduction.
Register in XPER Configuration Block:
Register
XPERCON
Description
XBUS peripheral control of XPER visibility
System Control Block
This block has several system management functions.
The System Control Block controls the system register write protection, introduced for
the system control registers SYSCON1-3.
Note: The new register write protection especially supports modularity of design, and is
therefore not compatible with the previously known C16x release function, using
the release bitfield in SYSCON2 for write protection.
Additional control functions of the System Control Block:
– Control of fast external interrupt inputs
– Control of external interrupt source selection
– Control of interrupt subnode for PLL and realtime clock interrupts
– Control of spike suppression for fast external interrupts and NMI in Sleep mode
– Clock output frequency control
The System Control Block provides the following registers: :
Register
SCUSLC
SCUSLS
EXICON
EXISEL
ISNC
FOCON
Description
SCU security level command register
SCU security level status and password register
External interrupt control register (see Chapter 7.8.1, page 125)
External interrupt source selection control register (see Chapter 7.8.2, page 126)
Interrupt subnode control register (see Chapter 7.8.3, page 127)
Frequency output control register
Data Sheet
461
2001-02-23