C165UTAH Datasheet, PDF (440/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
System Reset
C165UTAH
V_CC
RSTOUT
RSTIN
External
Hardware
Reset
+ ^b)
Figure 138 External Reset Circuitry
a) &
External
Reset
Sources
a) Generated Warm Reset
b) Automatic Power-ON Reset
MCA02259
Hardware Reset
A hardware reset is triggered when the reset input signal RSTIN is latched low. To
ensure the recognition of the RSTIN signal (latching), it must be held low for at least
8 CPU clock cycles.
Note: During reset, the CPU is clocked with the free-running PLL clock which may run
as slow as < 1 MHz.
Also shorter RSTIN pulses may trigger a hardware reset, if they coincide with the latch’s
sample point. However, it is recommended to keep RSTIN low for ca. 1 ms. After the
reset sequence has been completed, the RSTIN input is sampled. When the reset input
signal is active at that time the internal reset condition is prolonged until RSTIN gets
inactive.
During a hardware reset the PORT0 inputs for the reset configuration need some time
to settle on the required levels, especially if the hardware reset aborts a read operation
form an external peripheral. During this settling time the configuration may intermittently
be wrong. In such a case also the PLL clock selection may be wrong.
Note: To ensure a glitch free start-up of the C165UTAH, it is strongly recommended to
provide an external reset pulse of ca. 1 ms in order to allow the PLL to settle on
the desired CPU clock frequency.
The input RSTIN provides an internal pullup device equalling a resistor of 100 KΩ to
660 KΩ (the minimum reset time must be determined by the lowest value). Simply
connecting an external capacitor is sufficient for an automatic power-on reset, see b) in
Data Sheet
440
2001-02-23