C165UTAH Datasheet, PDF (421/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
Mode Register
Address: s_adr_x + 0E_H
Name: MODEH_x
IOM-2 Interface Controller
15 14 13 12 11 10 9 8
RPE
XPE
RES*
SRA
X
CRC
R
CRC
RES*
ITF
765
MDS
4 3 210
RES*
RAC
RES* =
RESERVED
Field
MDS
RAC
Bits Type Value Description
7:5 R/W 0
Mode Select
Determines the message transfer mode
of the HDLC controller, as shown in
Table 100.
3
R/W 0
Receiver Active
ITF
RCRC
8
R/W 0
10 R/W 0
The HDLC receiver is activated when this
bit is set to ’1’. If it is ’0’ the HDLC data is
not evaluated in the receiver.
Interframe Time Fill
Selects the inter-frame time fill signal
which is transmitted between HDLC-
frames.
0: Idle (continuous ’1’)
1: Flags (sequence of patterns: ‘0111
1110’)
Note: ITF must be set to ’0’ for power
down mode.
In applications with D-channel
access handling (collision
resolution), the only possible inter-
frame time fill is idle (continuous
’1’). Otherwise the D-channel on
the line interface can not be
accessed
Receive CRC
0: CRC is not stored in the RFIFO (i.e.
removed from incoming stream)
1: CRC is stored in the RFIFO
Data Sheet
421
2001-02-23