C165UTAH Datasheet, PDF (445/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
System Reset
Application-Specific Initialization Routine
After the internal reset condition is removed the C165UTAH fetches the first instruction
from location 00’0000_H, which is the first vector in the trap/interrupt vector table, the reset
vector. 4 words (locations 00’0000_H through 00’0007_H) are provided in this table to start
the initialization after reset. As a rule, this location holds a branch instruction to the actual
initialization routine that may be located anywhere in the address space.
Note: When the Bootstrap Loader Mode was activated during a hardware reset the
C165UTAH does not fetch instructions from location 00’0000_H but rather expects
data via serial interface ASC.
The first instruction is fetched from external memory. To decrease the number of
instructions required to initialize the C165UTAH, each peripheral is programmed to a
default configuration upon reset, but is disabled from operation. These default
configurations can be found in the descriptions of the individual peripherals.
During the software design phase, portions of the internal memory space must be
assigned to register banks and system stack. When initializating the stack pointer (SP)
and the context pointer (CP), it must be ensured that these registers are initialized before
any GPR or stack operation is performed. This includes interrupt processing, which is
disabled upon completion of the internal reset, and should remain disabled until the SP
is initialized.
Note: Traps (incl. NMI) may occur, even though the interrupt system is still disabled.
In addition, the stack overflow (STKOV) and the stack underflow (STKUN) registers
should be initialized. After reset, the CP, SP, and STKUN registers all contain the same
reset value 00’FC00_H, while the STKOV register contains 00’FA00_H. With the default
reset initialization, 256 words of system stack are available, where the system stack
selected by the SP grows downwards from 00’FBFE_H, while the register bank selected
by the CP grows upwards from 00’FC00_H.
Based on the application, the user may wish to initialize portions of the internal memory
before normal program operation. Once the register bank has been selected by
programming the CP register, the desired portions of the internal memory can easily be
initialized via indirect addressing.
At the end of the initialization, the interrupt system may be globally enabled by setting bit
IEN in register PSW. Care must be taken not to enable the interrupt system before the
initialization is complete.
The software initialization routine should be terminated with the EINIT instruction. This
instruction has been implemented as a protected instruction. Execution of the EINIT
instruction...
• disables the action of the DISWDT instruction,
• disables write accesses to register SYSCON,
Data Sheet
445
2001-02-23