C165UTAH Datasheet, PDF (407/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
Monitor Interrupt Status Register
Address: 58_H
Name: MOSR
IOM-2 Interface Controller
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
MDR MER MDA MAB
Field
MDR
MER
MDA
MAB
Reserved
Bits Type Value Description
3
R/W 0
MONITOR channel Data Received
2
R/W 0
MONITOR channel End of Reception
1
R/W 0
MONITOR Channel Data Acknowledge
The remote end has acknowledged the
MONITOR byte being transmitted.
0
R/W 0
MONITOR Channel Data Abort
15:4 R 0
These bits are reserved
Note: These interrupt status bits can be polled, i.e. a ’Read’ does not reset these
interrupts. To reset a specific interrupt a ’1’ must be written to the specific interrupt
bit.
Monitoring CDA Bits
Address: 5A_H
Name: MCDA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
MCDA21 MCDA20 MCDA11 MCDA10
Field
MCDA21
MCDA20
MCDA11
MCDA10
Bits Type Value Description
7:6 R 03 Monitoring CDAxy Bits
5:4 R 03 Bit 7 and Bit 6 of the CDAxy registers are
3:2 R 03 mapped into the MCDA register. This can
1:0 R 03 be used for monitoring the D-channel bits
on DU and DD and the ’Echo bits’ on the
TIC bus with the same register.
Data Sheet
407
2001-02-23