C165UTAH Datasheet, PDF (305/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
High-Speed Synchronous Serial Interface
SSCCON (FFB2_H / D9_H)
SFR
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC SSC
SSC SSC SSC SSC SSC
EN=1 MS ^- BSY BE PE RE TE ^-
-
-
-
SSCBC
rw rw - rw rw rw rw rw -
-
-
-
r
Bit
SSCBC
SSCTE
SSCRE
SSCPE
SSCBE
SSCBSY
SSCMS
SSCEN
Function (Operating Mode, SSCEN = ‘1’)
SSC Bit Count Field
Shift counter is updated with every shifted bit. Do not write to!!!
SSC Transmit Error Flag
1:
Transfer starts with the slave’s transmit buffer not being updated
SSC Receive Error Flag
1:
Reception completed before the receive buffer was read
SSC Phase Error Flag
1:
Received data changes around sampling clock edge
SSC Baudrate Error Flag
1:
More than factor 2 or 0.5 between Slave’s actual and expected
baudrate
SSC Busy Flag
Set while a transfer is in progress. Do not write to!!!
SSC Master Select Bit
0:
Slave Mode. Operate on shift clock received via SCLK.
1:
Master Mode. Generate shift clock and output it via SCLK.
SSC Enable Bit = ‘1’
Transmission and reception enabled. Access to status flags and M/S control.
Note: • The target of an access to SSCCON (control bits or flags) is determined by the
state of SSCEN prior to the access, ie. writing C057_H to SSCCON in programming
mode (SSCEN=’0’) will initialize the SSC (SSCEN was ‘0’) and then turn it on
(SSCEN=’1’).
• When writing to SSCCON, make sure that reserved locations receive zeros.
The shift register of the SSC is connected to both the transmit pin and the receive pin via
the pin control logic (see block diagram). Transmission and reception of serial data is
synchronized and takes place at the same time, ie. the same number of transmitted bits
is also received. Transmit data is written into the Transmit Buffer SSCTB. It is moved to
the shift register as soon as this is empty. An SSC-master (SSCMS=’1’) immediately
begins transmitting, while an SSC-slave (SSCMS=’0’) will wait for an active shift clock.
When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt request
(SSCTIR) will be generated to indicate that SSCTB may be reloaded again. When the
programmed number of bits (2...16) has been transferred, the contents of the shift
register are moved to the Receive Buffer SSCRB and a receive interrupt request
Data Sheet
305
2001-02-23