C165UTAH Datasheet, PDF (255/539 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165UTAH
Asynchronous/Synchr. Serial Interface
S0CON
Control Register
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
LB BRS ODD FDE OE
FE
PE
OEN
FEN
PEN/
RXDI
REN
STP
M
Field
M
STP
REN
PEN
RXDI
FEN
Bits Type Value Description
2-0 rwh
Mode Selection
0 0 0 8-bit data
synchronous operation
0 0 1 8-bit data
async. operation
0 1 0 IrDA mode, 8-bit data async. operation
0 1 1 7-bit data + parity
async. operation
1 0 0 9-bit data
async. operation
1 0 1 8-bit data + wake up bit async. operation
1 1 0 Reserved. Do not use this combination!
1 1 1 8-bit data + parity
async. operation
Bits are set/cleared by hardware after a
successfull autobaud detection operation.
Note: In synchronous operation (M=’000’), the
Fractional Divider is always disabled.
3
rw
Number of Stop Bit Selection
0
One stop bit
1
Two stop bits
4
rwh
Receiver Enable Control
0
Receiver diabled
1
Receiver enabled
Bit can be affected during autobaud detection
operation when bit ABEN_AUREN is set.
Bit is reset by hardware after reception of byte in
synchronous mode.
5
rw
Parity Check Enable /
IrDA Input Inverter Enable
All asynchronous modes without IrDA mode:
0
Ignore parity
1
Check parity
Only in IrDA mode (M=010):
0
RXD input is not inverted
1
RXD input is inverted
6
rw
Framing Check Enable (async. modes only)
0
Ignore framing errors
1
Check framing errors
Data Sheet
255
2001-02-23