HYB18L128160BF Datasheet, PDF (31/53 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 11 Timing Parameters for WRITE
Parameter
Symbol
- 7.5
Units
min.
max.
DQ and DQM input setup time
DQ and DQM input hold time
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
t_IS
1.5
t_IH
0.8
t_DQW
0
t_RC
67
t_RCD
19
t_RAS
45
t_WR
14
t_RP
19
–
ns
–
ns
–
t_CK
–
ns
–
ns
100k
ns
–
ns
–
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Notes
–
–
–
1)
1)
1)
1)
1)
CLK
Command ACT
t_RCD
NOP
t_RAS
t_RC
WRITE NOP
NOP
NOP
t_WR
NOP
PRE
t_RP
NOP
ACT
Address
Ba A,
Row x
A10 (AP) Row x
DQ
Ba A,
Col n
Dis
AP
DI n
DI n+1 DI n+2 DI n+3
Pre All
AP
Pre Bank A
Ba A,
Row b
Row b
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
Figure 25 WRITE Burst (CAS Latency = 2)
= Don't Care
CLK
t_RCD
Command ACT NOP
Address
Ba A,
Row n
A10 (AP)
Row
x
DQ
NOP
t_RAS
t_RC
WRITE NOP NOP
NOP
t_WR
NOP
PRE
NOP
Ba A,
Col n
Dis
AP
DI n DI n+1 DI n+2 DI n+3
Pre All
AP
Pre Bank A
t_RP
NOP ACT
Ba A,
Row b
Row
b
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
Figure 26 WRITE Burst (CAS Latency = 3)
= Don't Care
Data Sheet
31
V1.4, 2004-04-30