ICS9LPRS365BGLF Datasheet, PDF (9/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
33 VDDSRC_IO
34 SRCT4
35 SRCC4
36 GNDSRC
37 SRCT9
38 SRCC9
39 SRCC11/CR#_G
TYPE
PWR
I/O
I/O
PWR
OUT
OUT
I/O
DESCRIPTION
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of
SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte
6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
40 SRCT11/CR#_H
41 SRCT10
42 SRCC10
43 VDDSRC_IO
44 CPU_STOP#
45 PCI_STOP#
46 VDDSRC
47 SRCC6
48 SRCT6
I/O
OUT
OUT
PWR
IN
IN
PWR
OUT
OUT
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of
SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using
byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are
shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted
in from the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
1218—09/09/09
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