ICS9LPRS365BGLF Datasheet, PDF (20/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
Byte 0 FS Readback and PLL Selection Register
Bit Pin
Name
Description
Type
0
1
7-
6-
5-
4-
FSLC
FSLB
FSLA
iAMT_EN
CPU Freq. Sel. Bit (Most Significant)
R
CPU Freq. Sel. Bit
R
CPU Freq. Sel. Bit (Least Significant)
R
Set via SMBus or dynamically by CK505 if detects ^RW
dynamic M1
(Sticky
Bit)
See Table 1 : CPU Frequency Select
Table
Legacy Mode
iAMT Enabled
3
Reserved
Reserved
RW
2-
SRC_Main_SEL
Select source for SRC Main
RW SRC Main = PLL1 SRC Main = PLL3
1-
SATA_SEL
Select source for SATA clock
RW
SATA =
SRC_Main
SATA = PLL2
0-
PD_Restore
If config saved, on deassert return to last known
state else clear all config as if cold power on and go RW
to latches open state
Configuration Not
Saved
Configuration
Saved
Default
Latch
Latch
Latch
0
0
0
0
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin
7 13/14
6-
5
4 17/18
3
2
1
0
Name
SRC0_SEL
PLL1_SSC_SEL
Reserved
PLL3_CF3
PLL3_CF2
PLL3_CF1
PLL3_CF0
PCI_SEL
Description
Select SRC0 or DOT96
Select 0.5% down or center SSC
PLL3 Quick Config Bit 3
PLL3 Quick Config Bit 2
PLL3 Quick Config Bit 1
PLL3 Quick Config Bit 0
PCI_SEL
Type
R
RW
RW
RW
RW
RW
RW
RW
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1, , when 27_Select pin = 1, PWD = 0
0
SRC0
Down spread
1
DOT96
Center spread
See Table 2: pin17, 18 Configuration
Only applies if Byte 0, bit 2 = 0.
PCI from PLL1 PCI from PLL3
Default
Note 1
0
0
0
0
1
0
1
Byte 2 Output Enable Register
Bit Pin
Name
Description
7
REF_OE
Output enable for REF, if disabled output is tri-
stated
6
USB_OE
Output enable for USB
5
PCIF5_OE
Output enable for PCI5
4
PCI4_OE
Output enable for PCI4
3
PCI3_OE
Output enable for PCI3
2
PCI2_OE
Output enable for PCI2
1
PCI1_OE
Output enable for PCI1
0
PCI0_OE
Output enable for PCI0
Type
0
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Byte 3 Output Enable Register
Bit Pin
Name
7
SRC11_OE
6
SRC10_OE
5
SRC9_OE
4
SRC8/ITP_OE
3
SRC7_OE
2
SRC6_OE
1
Reserved
0
SRC4_OE
Description
Output enable for SRC11
Output enable for SRC10
Output enable for SRC9
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Reserved
Output enable for SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
1218—09/09/09
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