ICS9LPRS365BGLF Datasheet, PDF (1/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Recommended Application:
CK505 compliant clock with fully integrated voltage regulator
and Internal series resistor on differential outputs
Output Features:
• 2 - CPU differential low power push-pull pairs
• 9 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
• Integrated 33ohm series resistors on differential outputs,
Zo=50Ω
• Supports spread spectrum modulation, default is 0.5% down
spread
Pin Configuration
PCI0/CR#_A 1
64 SCLK
VDDPCI 2
63 SDATA
PCI1/CR#_B 3
62 REF0/FSLC/TEST_SEL
PCI2/TME 4
61 VDDREF
PCI3 5
60 X1
PCI4/27_Select 6
59 X2
PCI_F5/ITP_EN 7
58 GNDREF
GNDPCI 8
57 FSLB/TEST_MODE
VDD48 9
56 CK_PWRGD/PD#
USB_48MHz/FSLA 10
55 VDDCPU
GND48 11
54 CPUT0
VDD96_IO 12
53 CPUC0
SRCT0/DOTT_96 13
52 GNDCPU
SRCC0/DOTC_96 14
51 CPUT1_F
GND 15
50 CPUC1_F
VDDPLL3 16
49 VDDCPU_IO
27MHz_NonSS/SRCT1/SE1 17
48 NC
27MHz_SS/SRCC1/SE2 18
47 CPUT2_ITP/SRCT8
GND 19
46 CPUC2_ITP/SRCC8
VDDPLL3_IO 20
45 VDDSRC_IO
SRCT2/SATAT 21
44 SRCT7/CR#_F
SRCC2/SATAC 22
43 SRCC7/CR#_E
GNDSRC 23
42 GNDSRC
SRCT3/CR#_C 24
41 SRCT6
SRCC3/CR#_D 25
40 SRCC6
VDDSRC_IO 26
39 VDDSRC
SRCT4 27
38 PCI_STOP#
SRCC4 28
37 CPU_STOP#
GNDSRC 29
36 VDDSRC_IO
SRCT9 30
35 SRCC10
SRCC9 31
34 SRCT10
SRCC11/CR#_G 32
33 SRCT11/CR#_H
64-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
• Uses external 14.318MHz crystal, external crystal load 64-TSSOP
caps are required for frequency tuning
27_Select (power on latch)
0
1
• Selectable between one SRC differential push-pull pair
and two single-ended outputs
Pin13/14 & Pin17/18
DOT96, LCD_SS
Byte1 bit7 = 1.
SRC0, 27MHz Non SS & SS
Byte1 bit7 = 0.
Table 1: CPU Frequency Select Table
FSLC²
B0b7
FSLB¹
B0b6
FSLA¹
B0b5
CPU
MHz
SRC
MHz
PCI REF
MHz MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
1
0
200.00
1
166.66 100.00 33.33 14.318
1
0
0
333.33
1
0
1
100.00
1
1
1
1
0
400.00
1
Reserved
1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS} and V_{IH_FS} specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_LC is a three-level input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
USB
MHz
48.00
1218—09/09/09
DOT
MHz
96.00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.