ICS9LPRS365BGLF Datasheet, PDF (14/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
Long Accuracy
ppm
see Tperiod min-max values
-300
300
Clock period
T_period
33.33MHz output nominal
33.33MHz output spread
29.99100
30.00900
30.15980
Absolute min/max period
T_abs
33.33MHz output nominal/spread
Output High Voltage
V_OH
I_OH = -1 mA
Output Low Voltage
V_OL
I_OL = 1 mA
Output High Current
I_OH
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
Output Low Current
I_OL
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
Rising Edge Slew Rate
t_SLR
Measured from 0.8 to 2.0 V
Falling Edge Slew Rate
t_FLR
Measured from 2.0 to 0.8 V
Duty Cycle
d_t1
V_T = 1.5 V
Skew
t_{s k ew}
V_T = 1.5 V
Intentional PCI-PCI delay
t_delay
V_T = 1.5 V
Jitter, Cycle to cycle
t_{j c y c -c y c}
V_T = 1.5 V
*T_A = 0 - 70°C; V_DD = 3.3 V +/-5%
1_{Guaranteed by design and characterization, not 100% tested in production.}
29.49100 30.65980
2.4
0.4
-33
-33
30
38
1
4
1
4
45
55
250
200 nominal
500
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
3 _{See PCI Clock-to-Clock Delay Figure}
UNITS
ppm
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
%
ps
ps
ps
NOTES
1,2
2
2
2
1
1
1
1
1
1
1
1
1
1
1,3
1
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
1218—09/09/09
14