ICS9LPRS365BGLF Datasheet, PDF (7/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
MLF Pin Description
PIN #
PIN NAME
1 GNDREF
2 X2
3 X1
4 VDDREF
5 REF0/FSLC/TEST_SEL
6 SDATA
7 SCLK
8 PCI0/CR#_A
9 VDDPCI
10 PCI1/CR#_B
11 PCI2/TME
12 PCI3
13 PCI4/27_Select
14 PCI_F5/ITP_EN
15 GNDPCI
16 VDD48
ICS9LPRS365
Advance Information
TYPE
PWR
OUT
IN
PWR
I/O
I/O
IN
I/O
PWR
I/O
I/O
OUT
I/O
I/O
PWR
PWR
DESCRIPTION
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control
of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control
of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on
power-up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin24, 25 strap. On powerup, the logic value on
this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the
function talbe for the pin24 and pin25.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the
state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 53 and
54 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground for PCI clocks.
Power supply for USB clock, nominal 3.3V.
1218—09/09/09
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