ICS9LPRS365BGLF Datasheet, PDF (22/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
Byte 8 Device ID and Output Enable Register
Bit Pin
Name
Description
7
Device_ID3
Table of Device identifier codes, used for
6
5
4
Device_ID2
Device_ID1
Device_ID0
differentiating between CK505 package options,
etc.
3
Reserved
Reserved
2
Reserved
Reserved
Type
R
R
R
R
RW
RW
1
SE1_OE
Output enable for SE1
RW
0
SE2_OE
Output enable for SE2
RW
0
1
See Device ID Table
-
-
-
-
Disabled
Enabled
Disabled
Enabled
Default
1
1
0
1
0
0
27_Select
power on
latch
27_Select
power on
latch
Byte 9 Output Control Register
Bit Pin
7
6
5
4
Name
PCIF5 STOP EN
TME_Readback
REF Strength
Test Mode Select
Description
Allows control of PCIF5 with assertion of
PCI_STOP#
Truested Mode Enable (TME) strap status
Sets the REF output drive strength
Allows test select, ignores REF/FSC/TestSel
Type
RW
R
RW
RW
0
Free running
normal operation
1X (2Loads)
Outputs HI-Z
1
Stops with
PCI_STOP#
assertion
no overclocking
2X (3 Loads)
Outputs = REF/N
3
Test Mode Entry Allows entry into test mode, ignores FSB/TestMode RW Normal operation Test mode
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit) RW
See Table 3: V_IO Selection
1
IO_VOUT1
IO Output Voltage Select
RW
(Default is 0.8V)
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit) RW
Default
0
0
1
0
0
1
0
1
Byte 10 Free-Running Control Register
Bit Pin
Name
Description
7
27_Selec Latch read
back
6
Reserved
5
Reserved
Readback of 27_Select latch
Reserved
Reserved
4
CPU1_AMT_EN
M1 mode clk enable
3
Reserved
Reserved
2
CPU 2 Stop Enable
Enables control of CPU2 with CPU_STOP#
1
CPU 1 Stop Enable
Enables control of CPU1 with CPU_STOP#
0
CPU 0 Stop Enable
Enables control of CPU 0 with CPU_STOP#
Type
R
RW
RW
RW
RW
RW
RW
RW
0
Dot96/ LCD_SS
/SE
-
-
Disable
-
Free Running
Free Running
Free Running
1
SRC0/ 27MHz
-
-
Enable
-
Stoppable
Stoppable
Stoppable
Default
27_Select
latch
1
1
1
1
1
1
1
Byte 11 Strength Control Register
Bit Pin
Name
7
48MHz
6
PCIF5
5
PCI4
4
PCI3
3
PCI2
2
PCI1
1
PCI0
0
Reserved
Description
Reserved
Reserved
Type
0
RW
1x
RW
1x
RW
1x
RW
1x
RW
1x
RW
1x
RW
1x
RW
-
1
Default
2x
0
2x
0
2x
0
2x
0
2x
0
2x
0
2x
0
-
0
1218—09/09/09
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