ICS9LPRS365BGLF Datasheet, PDF (5/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
49
50
51
52
53
54
55
56
PIN NAME
VDDCPU_IO
CPUC1_F
CPUT1_F
GNDCPU
CPUC0
CPUT0
VDDCPU
CK_PWRGD/PD#
57
FSLB/TEST_MODE
58
GNDREF
59
X2
60
X1
61
VDDREF
62
REF0/FSLC/TEST_SEL
63
SDATA
64
SCLK
TYPE
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
DESCRIPTION
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and
Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in
test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable
test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
1218—09/09/09
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