ICS9LPRS365BGLF Datasheet, PDF (24/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
Byte 17 VCO Frequency Control Register PLL3
Bit Pin
Name
Description
7
N Div8
N Divider 8
6
N Div9
N Divider 9
5
M Div5
4
M Div4
The decimal representation of M Div (5:0) is equal
3
M Div3
to reference divider value. Default at power up =
2
M Div2
latch-in or Byte 0 Rom table.
1
M Div1
0
M Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 18 VCO Frequency Control Register PLL3
Bit Pin
Name
Description
7
N Div7
6
N Div6
5
N Div5
The decimal representation of N Div (9:0) is equal to
4
N Div4
VCO divider value. Default at power up = latch-in or
3
N Div3
Byte 0 Rom table.
2
N Div2
1
N Div1
0
N Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 19 Spread Spectrum Control Register PLL3
Bit Pin
Name
Description
7
SSP7
6
SSP6
5
SSP5
These Spread Spectrum bits will program the
4
SSP4
spread pecentage. Contact ICS for the correct
3
SSP3
values.
2
SSP2
1
SSP1
0
SSP0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 20 Spread Spectrum Control Register PLL3
Bit Pin
Name
Description
7
Reserved
Reserved
6
SSP14
5
SSP13
4
SSP12
These Spread Spectrum bits will program the
3
SSP11
spread pecentage. Contact ICS for the correct
2
SSP10
values.
1
SSP9
0
SSP8
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 21 M/N Enables
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
Description
RW
RW
RW
RW
RW
RW
RW
1
M/N Enable
CPU PLL M/N Enable
RW
0
M/N Enable
SRC/PCI PLL M/N Enable
RW
*These bits are disabled if TME is latched to 1
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
Disable
Disable
1
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
1
Enable
Enable
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
Default
0
x
X
X
X
X
X
X
Default
0
0
0
0
0
0
0
0
1218—09/09/09
24