ICS9LPRS365BGLF Datasheet, PDF (3/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
PIN NAME
17
27MHz_NonSS/SRCT1/SE1
18
27MHz_SS/SRCC1/SE2
19
GND
20
VDDPLL3_IO
21
SRCT2/SATAT
22
SRCC2/SATAC
23
GNDSRC
24
SRCT3/CR#_C
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
PWR
I/O
DESCRIPTION
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the power-up
default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See table 2 for more
information.
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential clock. See table 2 for
more information.
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
25
SRCC3/CR#_D
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4
pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
I/O
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
26
VDDSRC_IO
27
SRCT4
28
SRCC4
29
GNDSRC
30
SRCT9
31
SRCC9
32
SRCC11/CR#_G
PWR
I/O
I/O
PWR
OUT
OUT
I/O
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
1218—09/09/09
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