ICS9LPRS365BGLF Datasheet, PDF (12/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
Maximum Supply Voltage
VDDxxx
Core/Logic Supply
Maximum Supply Voltage
VDDxxx_IO
Low Voltage Differential I/O Supply
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
Case Temperature
V_IH
V_IL
Ts
Tcase
3.3V LVCMOS Inputs
Any Input
-
-
Input ESD protection
ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied, nor guaranteed.}
3 _{Maximum input voltage is not to exceed maximum VDD}
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
115
UNITS
V
V
V
V
°_C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
Ambient Operating Temp
Tambient
-
0
Supply Voltage
VDDxxx
Supply Voltage
3.135
Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
1
Input High Voltage
Input Low Voltage
Input Leakage Current
V_IHSE
V_ILSE
I_IN
Single-ended inputs
Single-ended inputs
V_IN = V_{DD ,} V_IN = GND
2
V_SS - 0.3
-5
Input Leakage Current
I_INRES
Inputs with pull or pull down resistors
V_IN = V_{DD ,} V_IN = GND
-200
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Low Threshold Input-
High Voltage (Test Mode)
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
V_OHSE
V_OLSE
V_OHDIF
V_OLDIF
V_{IH_FS_TEST}
V_{IH_FS}
V_{IL_FS}
Single-ended outputs, I_OH = -1mA
Single-ended outputs, I_OL = 1 mA
Differential Outputs, I_OH = TBD mA
Differential Outputs, I_OL = TBD mA
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
Operating Supply Current
I_{DD_DEFAULT}
I_{DD_PLL3DIF}
I_{DD_PLL3SE}
3.3V supply, PLL3 off
3.3V supply, PLL3 Differential Out
3.3V supply, PLL3 Single-ended Out
I_{DD_IO}
0.8V supply, Differential IO current,
all outputs enabled
Power Down Current
iAMT Mode Current
Input Frequency
Pin Inductance
Input Capacitance
Spread Spectrum Modulation
Frequency
I_{DD_PD3.3}
I_{DD_PDIO}
I_{DD_iAMT3.3}
I_{DD_iAMT0.8}
F_i
L_pin
C_IN
C_OUT
C_INX
f_SSMOD
3.3V supply, Power Down Mode
0.8V IO supply, Power Down Mode
3.3V supply, iAMT Mode
0.8V IO supply, iAMTMode
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
Triangular Modulation
*T_A = 0 - 70°C; V_DD = 3.3 V +/-5%
1_{Guaranteed by design and characterization, not 100% tested in production.}
2.4
0.7
2
0.7
V_SS - 0.3
25
1.5
30
TYPICAL
MAX
70
3.465
3.465
V_DD + 0.3
0.8
5
200
0.4
0.9
0.4
V_DD + 0.3
1.5
0.35
95
250
106
250
101
250
32
80
26
30
0.23
0.5
47
80
5
10
14.318
7
5
6
5
33
UNITS
°C
V
V
V
V
uA
uA
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
kHz
Notes
1,2
1,2
1,2,3
1,2
1,2
1,2
1,2
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1218—09/09/09
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