ICS9FG1201H_11 Datasheet, PDF (9/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
SMBusTable: Gear Ratio Select Register
Byte 0 Pin #
Name
Control Function
Bit 7 DIF(9:0)
Group of 10 gear ratio enable
Bit 6 DIF(11:10)
Group of 2 gear ratio enable
Bit 5
-
Reserved
Bit 4
-
Gear Ratio FS4 (FS_A_410)
Bit 3
-
Gear Ratio FS3
Bit 2
-
Gear Ratio FS2
Bit 1
-
Gear Ratio FS1
Bit 0
-
Gear Ratio FS0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Gear Ratio
1:1
Gear Ratio
1:1
See 9FG1201
Programmable Gear
Ratios Table
PWD
1
1
1
Latch
1
0
1
1
SMBusTable: Output Control Register
Byte 1 Pin #
Name
Bit 7 35, 36
DIF_7
Bit 6 32, 33
DIF_6
Bit 5 24, 25
DIF_5
Bit 4
19,20
DIF_4
Bit 3
16,17
DIF_3
Bit 2
13,14
DIF_2
Bit 1
9,10
DIF_1
Bit 0
6,7
DIF_0
Control Function Type
0
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
Output Control
RW
Hi-Z
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBusTable: Output and PLL BW Control Register
Byte 2 Pin #
Name
Control Function Type
0
Bit 7
Reserved
Bit 6 see note
PLL_BW# adjust
RW High BW
Bit 5 see note
BYPASS# test mode / PLL
RW Bypass
Bit 4
Reserved
Bit 3
51,52
DIF_11
Output Control
RW
Hi-Z
Bit 2
47,48
DIF_10
Output Control
RW
Hi-Z
Bit 1
42,43
DIF_9
Output Control
RW
Hi-Z
Bit 0
39,40
DIF_8
Output Control
RW
Hi-Z
Note: Bit 6 is wired OR to the pin 1 input, any 0 selects High BW
Note: Bit 5 is wired OR to the pin 30 input, any 0 selects Fanout Bypass mode
1
Low BW
PLL
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBusTable: Output Enable Readback Register
Byte 3 Pin #
Name
Control Function
Bit 7
34
Readback - OE7# Input
Bit 6
31
Readback - OE6# Input
Bit 5
26
Readback - OE5# Input
Bit 4
21
Readback - OE4# Input
Bit 3
18
Readback - OE3# Input
Bit 2
15
Readback - OE2# Input
Bit 1
8
Readback - OE1# Input
Bit 0
5
Readback - OE0# Input
Type
R
R
R
R
R
R
R
R
0
1
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
PWD
X
X
X
X
X
X
X
X
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
9
1371F — 09/23/09